Lead Memory Architect/Designer ID#5216
Silicon Valley, CA
We are currently seeking a Lead Memory Architect/Designer for our client, who is a global leader and innovator in telecommunications. This role is located in Silicon Valley and offers a compensation package which includes $140-165k base salary plus relocation, Visa sponsorship, bonus and benefits.
is seeking a Memory architect and designer for complex memory sub-systems in multi-core DSP and CPU systems
• Responsible for developing architecture and design of a memory management unit including L1 and L2 cache memories
• Makes recommendations and decisions regarding the technical aspects of assigned projects
• Works with the DSP/CPU architect, designers, system architects to analyze memory sub-system performance, and propose new architectures and designs to improve the performance and reduce power
• MS with 10 years of experience or PhD with 7 years of experience in CPU/DSP verification and memory sub-system or equivalent education and directly related experience
• Detailed knowledge of complex memory architectures and design techniques in multi-core SOC designs in deep submicron technologies
• In depth knowledge of high performance memory system and interconnect architectures
• Detailed understanding of cache coherency protocols and experienced in memory cache design implementation, DMA, and memory access hardware and memory protection
• In-depth knowledge and experience with low power design techniques and performance/power trade offs
• Excellent communication skills with ability to articulate complex technical issues and directions to team members
• Ability to work in large, cross functional and geographically dispersed teams.
• Demonstrated organizational, planning, and analytical skills
• Demonstrated business communications skills (verbal, written and presentation)
• 140 – 165K
If you are interested in this role or know someone who please forward resumes to email@example.com
An Equal Opportunity Employer, m/f/d/v.
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